1. Field of the Invention
The present invention relates to a DRAM cell and, more particularly, to a DRAM cell and a method of fabricating the same, in which the DRAM cell is formed having a vertical structure in order to decrease the number of fabrication steps while increasing packing density.
2. Discussion of Related Art
Generally, a DRAM cell having a horizontal structure consists of one bit line, one word line, one access transistor and one storage capacitor. The gate of the access transistor is connected to the word line, and its drain is connected to the bit line. Various structures of DRAM cell arrays have been proposed in order to increase the packing density of the DRAM.
A conventional DRAM cell will be explained below with reference to FIG. 1. FIG. 1 is a cross-sectional view of the conventional DRAM cell structure. As shown in FIG. 1, the conventional DRAM cell is constructed in such a manner that a p-type well 11 is formed in an n-type semiconductor substrate 10, a gate electrode 13 is formed on an active region of p-type well 11 and is insulated from the active region by a gate oxide layer 12.
The conventional DRAM cell further includes a gate cap oxide layer 14, sidewall oxide layer 15, drain and source regions 16a and 16b formed in a portion of p-type well 11 placed on both sides of gate electrode 13, and a first interlevel insulating layer 17 formed on the overall surface of the substrate including gate electrode 13.
The first interlevel insulating layer 17 has a first contact hole exposing the drain region 16a. Furthermore, a bit line 19 for transmitting data is formed on first interlevel insulating layer 17, and is electrically connected to drain region 16a via the contact hole. Second and third interlevel insulating layers 21 and 22 are formed over the substrate 10. Second and third interlevel insulating layers 21 and 22 have a second contact hole formed therein exposing source region 16b. Moreover, a capacitor storage electrode 23 is formed on third interlevel insulating layer 22 and is electrically connected to source region 16b through the second contact hole. The capacitor storage electrode 23 has a protrusion at both its edges. A dielectric layer 24 is formed on the capacitor storage electrode 23, and a capacitor plate electrode 25 is formed on dielectric layer 24. Also, as shown in FIG. 1, sidewall insulating layers 18a and 18b are formed on the inner sidewall of the first and second contact holes, respectively, and the bit line 19 has a double structure with a conductive layer 20 laminated thereon.
In the aforementioned conventional DRAM cell, the source region 16b, the drain region 16a, and channel region therebetween are formed horizontally, and the gate oxide layer 12 and gate electrode 13 are formed on the channel region. The conventional DRAM cell has the following problems. First, when the conventional DRAM cell structure is applied to a highly integrated device, the short channel effect is increased since the source region, drain region and channel region are formed horizontally. Also, the capacitance is reduced if the size of the DRAM cell is decreased.
Secondly, the bit line and capacitor are sequentially formed to contact the source and drain regions of the transistor, respectively. This makes the photolithography processes complicated. Also, it is difficult to secure a margin of error during the photolithography processes.